A memory cell of DRAM usually comprises a metal oxide semiconductor (MOS) transistor or metal insulator semiconductor (MIS) transistor and a capacitor. The cell capacitance is determined by the amount of charge stored in the capacitor. Accordingly, in order to provide a sufficient memory cell capacitance even if the memory cell area of the DRAM is reduced, formation of capacitors in grooves which are referred to as trenches in a semiconductor substrate has been recently used. Formation of capacitors around pillars which are left in the subsurface of the semiconductor substrate after etching has been proposed.
The memory cells including the trenches are classified into a trench capacitor structure type in which an inner surface portion of the trench acts as a charge storage node and a polysilicon portion embedded in the trench with an insulator film being intermediate therebetween acts as an opposite electrode and a so-called stacked trench structure type in which a charge storage electrode which is a storage node is formed on an insulator film within the trench and an opposite electrode is formed with a dielectric film disposed on the charge storage electrode.
For example, an improved stacked trench structure is disclosed in Tsukamoto et al. "Double Stacked Capacitor with Self-aligned Poly Source/Drain Transistor (DSP) Cell for Megabit DRAM", PP328-331 IEDM 87 IEEE 1987.
The above mentioned trenches have been heretofore formed by etching a semiconductor substrate.
Processes for producing a memory cell having a trench structure are disclosed in JP-A-02-111062 (Yamada et al) and JP-A-63-253660 (Kiyosumi). A method of forming trenches for trench capacitors is disclosed in JP-A-01-105567 (Motoyama et al).
If trenches are formed in a semiconductor substrate by etching, a number of crystal defects are generated in the semiconductor substrate around the trenches due to etching damage. In the trench capacitor structure in which a charge storage node is defined in the inner surface region of the trench, a leak current may easily conduct, resulting in deterioration of data holding characteristics.
If a device having a reduced memory cell area is formed in order to overcome the problems due to etching damages or the leak current, the data holding capability is further lowered, resulting in that integration degree of devices can not be increased above a predetermined value.
If an etching method having a high fabrication accuracy is adopted to form a finer pattern, etching damages become more serious since a high energy ion assist is needed.